搜索资源列表
fpga_uart
- verilog编写的简单串口收发代码，quartues II 下cyclone II 测试通过-prepared by the simple serial transceiver verilog code, quartues II test under the cyclone II
LCD_test
- this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
FT245BL_test
- this a example for the mouse vga for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
DE2_TVdecoder
- 基于altera cyclone ii的TV译码例程-demonstrations about TV decoder based on altera cyclone ii
yinpinxinhaofenxiyi1233412
- 基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核的基于FFT的音频信号分析仪-Based on Altera Cyclone II series FPGA embedded high-performance embedded IP core (Nios) soft core processor FFT-based audio signal analyzer
SDRAM_CONTROL_DE2
- 基于Altera公司的Cyclone II 2C35芯片和SDRAM芯片IS42S16400的sdram控制器（教学用）-Based on Altera Cyclone II 2C35 chips and SDRAM chips IS42S16400. the code realize a the sdram controller (for teaching)
uCOS-II-Cyclone-V-SoC
- 应用在ALTERA FPGA芯片的UCOS开发板实现代码,从micrium官网下载-μC/OS-II Example for the Cyclone V SoC Development Kit
ASS2_bench
- Verilog HDL for IRDA transmitter by DE2 board using Altera Cyclone II Quartus-Verilog HDL for IRDA transmitter by DE2 board using Altera Cyclone II QuartusII
EX4V1.1
- 该设计是基于Verilog HDL的秒表。此设计是在Altera的Cyclone II系列的FPGA上验证过了。能够实现精确计时。-This design is a stopwatch based on the Verilog HDL. And it has been verified on the platform of Cyclone II s FPGA of Altera. Finally it can achieve accurate timing.
audio_latest.tar
- Audio Codec(ADPCM 1-Bit) The code is ready for Altera Cyclone-II DE1 Starter board and it is tested, you can modify codes and use them in any project. Core Descr iption: Sampling Frequency: 44100Hz Channels: Stereo Bit-rate: 1 Bit Per Sa
FIFO_altera.v
- FIFO for Altera Cyclone II or Cyclone III on memory blocks. Length of FIFO can be changed.
FFT
- 基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核,实现了基于FFT的音频信号分析-Altera Cyclone II FPGA family based embedded high-performance embedded IP core (Nios) soft core processor to achieve a FFT-based audio signal analysis
digital_clk
- VHDL Code for a digital bit clock counter and 7 segment display clock on a altera DE2 board with a cyclone II FPGA
hex7segb
- Implimentation of the switches and 7 segment display bit counter on an Altera DE2 baord via VHDL code on the Cyclone II FPGA
dwn_sampler
- Multirate digital signal processing system which includes sampling rate conversion. This technique is necessary for systems with different input and output sampling rates, as the proposed multirate device is downsampler FPGA implementation of
rapport_vhdl
- Projet fréquencemetre réalisé en VHDL et implimenté sur la carte FPGA Cyclone -Projet fréquencemetre réalisé en VHDL et implimenté sur la carte FPGA Cyclone II
vga_test
- 基于nios的vga控制器,分辨率及显示区域,显示位数,显存深度可调整,已经在altera cyclone ii条件下测试通过 quartus13.0开发环境 主机端符合avalon标准-VGA controller based on NIOS, resolution and display area show the median, the memory depth can be adjusted, has been in Altera cyclone II under the conditi
pwm
- VHDL, quartet 2 , FPGA, cyclone II, controllen PWM brightness
DE2-115 Ephoto
- The 4.3" Ultra-high Resolution LCD Touch Panel Development Kit provides users a 800x480 full-color high-quality LCD Touch Panel with complete reference designs and source code allowing users to develop applications by a touch panel on the Altera
verilog
- 《数字信号处理的FPGA实现（第三版）》作者：U.Meyer-Baese 的配套源码，基于quartus9.0编写，使用的cyclone ii。其中包含FIR IIR FFT等算法的实现，对学习图像处理很有帮助。- FPGA digital signal processing (third edition) Author: U.Meyer-Baese The matching source, based on quartus9.0 preparation, the use of cyc